The present invention relates to a non-volatile split gate EPROM memory cell and self-aligned field insulation process for obtaining the above cell.
The use is known of non-volatile split gate EPROM memory cells. In such cells the floating gate does not extend along the entire channel of the cell, but only covers a part of it to form the actual memory cell. The second part of the channel is governed directly by the control gate which thus goes to form a small transistor in series with the cell itself.
A first advantage deriving from the use of the split gate memory cell consists in the fact that with such a structure the problem is highlighted of the partial raising of the floating gate voltage (with consequent current in the channel) due to the capacitive coupling between floating gate and drain (a problem known as &lt;&lt;drain turn-or&gt;&gt;), when the drain is biased at a high voltage and the control gate is grounded. In fact in a split gate cell, even in the case when the capacitive coupling between the floating gate and the drain is large, the opening of the channel is completely prevented by the presence of the transistor in series with the cell itself.
A second advantage deriving from the use of the above memory cell consists in the fact that, thanks to its asymmetry, it can be programmed starting from only one of the two diffusions (the one known as the drain, that is, that facing the floating gate). If the cell is read from the source side (that is, by raising above ground the diffusion from which writing is impossible), it is then possible to abolish completely the so-called &lt;&lt;soft-writing&gt;&gt; problem, that is, of the slow and undesired programming of the cell during its reading step.
As a result of this advantage the voltage at which the bit-line diffusion is polarised during the reading step of the cell itself can be raised with respect to the typical value used (about 1 volt), thus obtaining both an increase in the cell's reading current and a drop in the capacity of the bit-line itself.
Several types of split gate EPROM memory cells are known in the literature.
A first example of a cell of this type is described in the U.S. Pat. No. 4,328,565 and consists of a non self-aligned structure, in which the source and drain diffusions are implanted before the definition of the superimposed floating and control gates,
It follows that, for the drain diffusion to be coupled to the floating gate (that is, sufficiently superimposed over it) independently of the mis-alignments between the different masks, it is necessary to maintain a large superimposition between the floating gate itself and the drain, from which there derives a large and highly variable capacitive coupling between the latter.
During the cell's programming step this is reflected in a wide variability of the value of the voltage transferred to the floating gate and thus in a threshold jump, after the writing step, whose value is predictable with difficulty and a function of the process misalignments,
A second problem related to this cell is connected with the fact of executing the diffusion implant before growing the subsequent oxide layers of gate and interpoles, The diffusions are subjected in this way to all the heat treatments connected with these oxidation steps and they are thus deper and more diffuse, This is the opposite of the current tendency towards new generations of processes characterised by an increasingly higher density.
A last problem related to this type of cell is connected with the fact that the control gate passes over the gate and drain diffusions, it being insulated from them only by a thin layer of thermal oxide. It follows that the word-line capacity is raised with a corresponding reduction in the speed of the device.
A second example of cell of this type is described in U.S. Pat. No. 4,639,893.
In this cell the drain diffusion is self-aligned with the floating gate; the source and drain implant is executed after defining the floating gate itself and, on the drain, it is self-aligned with it, The capacitive coupling of the floating gate with the drain thus becomes independent from the process misalignments,
The distance between source and drain, on the other hand, is subject to the misalignment between the mask which defines the floating gate and that used for the source and drain implant.
As in the cell of the first example, the control gate passes completely over the source and drain diffusion and it is insulated from it only by a thin oxide thermally grown simultaneously with the gate oxide and with the interpoly one,
The greatest problem of this type of structure is precisely in this oxidation step; to lower the word-line's capacity (and thus to raise the access speed of the device) it is in fact necessary for the thin oxide to be as thick as possible, but this is not reconcilable with a good quality of the other two oxides, To obtain an appreciable difference between the thicknesses of these oxides it is in actual fact necessary to execute oxidation at low temperatures, but the oxides so obtained are of poor quality.